Abstract
A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global C1G2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator, a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0.18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of -108 dBc/Hz and -129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.
| Original language | English |
|---|---|
| Pages (from-to) | 408-412 |
| Number of pages | 5 |
| Journal | Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics |
| Volume | 30 |
| Issue number | 3 |
| State | Published - Sep 2010 |
Keywords
- Frequency synthesizer
- Phase noise
- UHF RFID
- ΔΣ modulator