A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

Tianye He; Runxi Zhang; Hui Yang; Jiefu Wang; Chunqi Shi

doi:10.1109/ISCAS.2018.8351240

A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

Tianye He
, Runxi Zhang
, Hui Yang
, Jiefu Wang
, Chunqi Shi

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351240
State	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 27 May 2018 → 30 May 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18

Keywords

Dual co-tuning
PLL
low RMS jitter
wide LR

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10.1109/ISCAS.2018.8351240

Cite this

He, T., Zhang, R., Yang, H., Wang, J., & Shi, C. (2018). A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351240 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351240

He, Tianye ; Zhang, Runxi ; Yang, Hui et al. / A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9\% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications",

abstract = "This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9\% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.",

keywords = "Dual co-tuning, PLL, low RMS jitter, wide LR",

author = "Tianye He and Runxi Zhang and Hui Yang and Jiefu Wang and Chunqi Shi",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

month = apr,

day = "26",

doi = "10.1109/ISCAS.2018.8351240",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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He, T, Zhang, R, Yang, H, Wang, J & Shi, C 2018, A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351240, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351240

A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. / He, Tianye; Zhang, Runxi; Yang, Hui et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351240 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

AU - He, Tianye

AU - Zhang, Runxi

AU - Yang, Hui

AU - Wang, Jiefu

AU - Shi, Chunqi

PY - 2018/4/26

Y1 - 2018/4/26

N2 - This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.

AB - This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.

KW - Dual co-tuning

KW - PLL

KW - low RMS jitter

KW - wide LR

UR - https://www.scopus.com/pages/publications/85057100360

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DO - 10.1109/ISCAS.2018.8351240

M3 - 会议稿件

AN - SCOPUS:85057100360

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

He T, Zhang R, Yang H, Wang J, Shi C. A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8351240. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2018.8351240

A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

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