TY - JOUR
T1 - A High-Precision Programmable Delay Circuit with Ultra-Wide Range ( μs-Tens of Seconds)
AU - Zhang, Xiaohui
AU - Rong, Xueyan
AU - Wang, Xueping
AU - Li, Zhipei
AU - Diao, Shengxi
N1 - Publisher Copyright:
© 2025 World Scientific Publishing Company.
PY - 2025
Y1 - 2025
N2 - In this paper, a novel programmable delay circuit with ultra-wide delay range and high precision is proposed for automatic control systems. This circuit is based on counting the specified number of periods of relaxation oscillator (ROSC) to generate the precise delay. To achieve the ultra-wide delay, wide-range ROSC and programmable digital control cell are adopted. Utilizing good frequency linearity of ROSC, delay with high precision is realized. A detailed theoretical analysis of delay error is derived. Compared with the conventional method, such as the timer of field programmable gate array (FPGA), this circuit features low power consumption, compact area and vibration immunity. Implemented in 0.18-μm CMOS process, a prototype of the proposed delay circuit occupies an area of 1.27×0.46 mm and consumes 211 μA current at 800KωRSET. With a supply voltage range of 2.25-5.5V, the measured delay range is from 2.0417 μs to 31.7366s, and the normalized delay error variation with VDD is 0.18%. In the delay intervals of 1.9-15.2 μs, 15.2-972.8 μs and beyond 972.8 μs, the measured values of normalized delay error without fixed error are less than 4.3%, 1% and 0.75%, respectively. Besides, the method to adjust the delay time is effortless, which is easy to use.
AB - In this paper, a novel programmable delay circuit with ultra-wide delay range and high precision is proposed for automatic control systems. This circuit is based on counting the specified number of periods of relaxation oscillator (ROSC) to generate the precise delay. To achieve the ultra-wide delay, wide-range ROSC and programmable digital control cell are adopted. Utilizing good frequency linearity of ROSC, delay with high precision is realized. A detailed theoretical analysis of delay error is derived. Compared with the conventional method, such as the timer of field programmable gate array (FPGA), this circuit features low power consumption, compact area and vibration immunity. Implemented in 0.18-μm CMOS process, a prototype of the proposed delay circuit occupies an area of 1.27×0.46 mm and consumes 211 μA current at 800KωRSET. With a supply voltage range of 2.25-5.5V, the measured delay range is from 2.0417 μs to 31.7366s, and the normalized delay error variation with VDD is 0.18%. In the delay intervals of 1.9-15.2 μs, 15.2-972.8 μs and beyond 972.8 μs, the measured values of normalized delay error without fixed error are less than 4.3%, 1% and 0.75%, respectively. Besides, the method to adjust the delay time is effortless, which is easy to use.
KW - normalized delay error
KW - Programmable delay circuit
KW - relaxation oscillator
KW - ultra-wide delay range
UR - https://www.scopus.com/pages/publications/105016742456
U2 - 10.1142/S0218126625504651
DO - 10.1142/S0218126625504651
M3 - 文章
AN - SCOPUS:105016742456
SN - 0218-1266
JO - Journal of Circuits, Systems and Computers
JF - Journal of Circuits, Systems and Computers
M1 - 2550465
ER -