A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission

  • Liangjian Lyu
  • , Dawei Ye*
  • , Rongjin Xu
  • , Geng Mu
  • , Heng Zhao
  • , Yingfei Xiang
  • , Yuting Tu
  • , Yiyun Zhang
  • , C. J. Richard Shi
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

This brief presents a 64-channel fully-integrated wireless neural interfacing SoC implemented in a 65 nm CMOS process. To minimize the weight and size of the head-stage connected to the small experimental animals, the system is designed to be powered by either a single-coil 13.56 MHz wireless power receiver or a small-sized button cell battery. A replica-biased 0.35 V 110 dB PSRR LNA is introduced to tolerate the power supply noise inherently in wireless power harvesting and save power consumption. The recorded neural data is transmitted wirelessly by a 2.4/3.2 GHz dual-band OOK transmitter, which supports 54 Mb/s symbol rate, 44 pJ/bit meter-range wireless data transmission. To reduce the transmission BER, forward error correction with convolutional code and cyclic redundancy code is adopted.

Original languageEnglish
Article number9043581
Pages (from-to)831-835
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume67
Issue number5
DOIs
StatePublished - May 2020
Externally publishedYes

Keywords

  • ADC
  • CMRR
  • Neural interface
  • PSRR
  • analog front-end~(AFE)
  • wireless power transfer~(WPT)
  • wireless transmitter

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