TY - GEN
T1 - A Discrete-Time Delta-Sigma Modulator with Low Power and High Resolution
AU - Yan, Xiaofeng
AU - Diao, Shengxi
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This article presents a discrete-time third-order three-bit delta-sigma modulator (DSM) with the cascade-of- integrators feedforward (CIFF) topology, specifically designed for biological signal conversion in wearable medical devices. Within this modulator, a two-step adder is employed to facilitate the precise addition of analog signals while simultaneously mitigating the design requirements for the operational amplifier. To address the nonlinearity in multi-bit digital-to- analog converters (DACs), the data weighting averaging (DWA) digital calibration circuit is implemented. According to the post- simulation results, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 111.3 dB over a 1 kHz signal bandwidth, with a sampling frequency of 1.024 MHz. It operates with a power consumption of 0.52 mW from a 1.8 V supply, resulting in a Schreier figure of merit (FoM) of 174.1 dB.
AB - This article presents a discrete-time third-order three-bit delta-sigma modulator (DSM) with the cascade-of- integrators feedforward (CIFF) topology, specifically designed for biological signal conversion in wearable medical devices. Within this modulator, a two-step adder is employed to facilitate the precise addition of analog signals while simultaneously mitigating the design requirements for the operational amplifier. To address the nonlinearity in multi-bit digital-to- analog converters (DACs), the data weighting averaging (DWA) digital calibration circuit is implemented. According to the post- simulation results, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 111.3 dB over a 1 kHz signal bandwidth, with a sampling frequency of 1.024 MHz. It operates with a power consumption of 0.52 mW from a 1.8 V supply, resulting in a Schreier figure of merit (FoM) of 174.1 dB.
KW - Delta-sigma modulator
KW - cascade-of-integrators feedforward (CIFF)
KW - data weighting averaging (DWA)
KW - two-step adder
UR - https://www.scopus.com/pages/publications/105000888450
U2 - 10.1109/CISP-BMEI64163.2024.10906130
DO - 10.1109/CISP-BMEI64163.2024.10906130
M3 - 会议稿件
AN - SCOPUS:105000888450
T3 - Proceedings - 2024 17th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, CISP-BMEI 2024
BT - Proceedings - 2024 17th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, CISP-BMEI 2024
A2 - Li, Qingli
A2 - Wang, Yan
A2 - Wang, Lipo
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, CISP-BMEI 2024
Y2 - 26 October 2024 through 28 October 2024
ER -