A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation

Xiao Jin Li; Jun Feng Tang; Gang Zhang; Zong Sheng Lai

doi:10.1109/ICSICT.2012.6466670

A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation

Xiao Jin Li^*
, Jun Feng Tang
, Gang Zhang
, Zong Sheng Lai

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A novel ROM-less direct digital frequency synthesizer (DDFS) is presented using phase to sinusoid amplitude conversion blocks based on optimized sixth-order polynomial approximation. A slide factor ξ≈0.703 is introduced to separate 0-90 phase degree into two parts, which are further approximated with a sixth-order even polynomial. The mathematic analysis shows that the maximum residual 1.05e-6 can be achieved, thus an output resolution up to 20 bits can be gotten. Furthermore, the computational units of the polynomial approximation have been decomposed into twenty-six stages to support a 330MHz clock rate. The spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is up to 138 dBc.

Original language	English
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6466670
State	Published - 2012
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 29 Oct 2012 → 1 Nov 2012

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	29/10/12 → 1/11/12

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10.1109/ICSICT.2012.6466670

Cite this

Li, X. J., Tang, J. F., Zhang, G., & Lai, Z. S. (2012). A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Article 6466670 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6466670

Li, Xiao Jin ; Tang, Jun Feng ; Zhang, Gang et al. / A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation. ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{0c2040fa9f534a71b3b204b07e5ecfa1,

title = "A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation",

abstract = "A novel ROM-less direct digital frequency synthesizer (DDFS) is presented using phase to sinusoid amplitude conversion blocks based on optimized sixth-order polynomial approximation. A slide factor ξ≈0.703 is introduced to separate 0-90 phase degree into two parts, which are further approximated with a sixth-order even polynomial. The mathematic analysis shows that the maximum residual 1.05e-6 can be achieved, thus an output resolution up to 20 bits can be gotten. Furthermore, the computational units of the polynomial approximation have been decomposed into twenty-six stages to support a 330MHz clock rate. The spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is up to 138 dBc.",

author = "Li, \{Xiao Jin\} and Tang, \{Jun Feng\} and Gang Zhang and Lai, \{Zong Sheng\}",

year = "2012",

doi = "10.1109/ICSICT.2012.6466670",

language = "英语",

isbn = "9781467324724",

series = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

booktitle = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 ; Conference date: 29-10-2012 Through 01-11-2012",

}

Li, XJ, Tang, JF, Zhang, G & Lai, ZS 2012, A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6466670, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 29/10/12. https://doi.org/10.1109/ICSICT.2012.6466670

A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation. / Li, Xiao Jin; Tang, Jun Feng; Zhang, Gang et al.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6466670 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation

AU - Li, Xiao Jin

AU - Tang, Jun Feng

AU - Zhang, Gang

AU - Lai, Zong Sheng

PY - 2012

Y1 - 2012

N2 - A novel ROM-less direct digital frequency synthesizer (DDFS) is presented using phase to sinusoid amplitude conversion blocks based on optimized sixth-order polynomial approximation. A slide factor ξ≈0.703 is introduced to separate 0-90 phase degree into two parts, which are further approximated with a sixth-order even polynomial. The mathematic analysis shows that the maximum residual 1.05e-6 can be achieved, thus an output resolution up to 20 bits can be gotten. Furthermore, the computational units of the polynomial approximation have been decomposed into twenty-six stages to support a 330MHz clock rate. The spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is up to 138 dBc.

AB - A novel ROM-less direct digital frequency synthesizer (DDFS) is presented using phase to sinusoid amplitude conversion blocks based on optimized sixth-order polynomial approximation. A slide factor ξ≈0.703 is introduced to separate 0-90 phase degree into two parts, which are further approximated with a sixth-order even polynomial. The mathematic analysis shows that the maximum residual 1.05e-6 can be achieved, thus an output resolution up to 20 bits can be gotten. Furthermore, the computational units of the polynomial approximation have been decomposed into twenty-six stages to support a 330MHz clock rate. The spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is up to 138 dBc.

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DO - 10.1109/ICSICT.2012.6466670

M3 - 会议稿件

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SN - 9781467324724

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BT - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

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Li XJ, Tang JF, Zhang G, Lai ZS. A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6466670. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2012.6466670

A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation

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