A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver

Hang Zhou; Bingyi Ye; Weixin Gai

doi:10.1109/ICICM56102.2022.10011239

A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver

Hang Zhou, Bingyi Ye, Weixin Gai

Peking University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.

Original language	English
Title of host publication	2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	377-381
Number of pages	5
ISBN (Electronic)	9781665460439
DOIs	https://doi.org/10.1109/ICICM56102.2022.10011239
State	Published - 2022
Externally published	Yes
Event	7th International Conference on Integrated Circuits and Microsystems, ICICM 2022 - Xi'an, China Duration: 28 Oct 2022 → 31 Oct 2022

Publication series

Name	2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022

Conference

Conference	7th International Conference on Integrated Circuits and Microsystems, ICICM 2022
Country/Territory	China
City	Xi'an
Period	28/10/22 → 31/10/22

Keywords

DC offset
clock delivery
quadrature error canceller
wireline transceiver

Access to Document

10.1109/ICICM56102.2022.10011239

Cite this

Zhou, H., Ye, B., & Gai, W. (2022). A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver. In 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022 (pp. 377-381). (2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICM56102.2022.10011239

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title = "A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver",

abstract = "With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.",

keywords = "DC offset, clock delivery, quadrature error canceller, wireline transceiver",

author = "Hang Zhou and Bingyi Ye and Weixin Gai",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022 ; Conference date: 28-10-2022 Through 31-10-2022",

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doi = "10.1109/ICICM56102.2022.10011239",

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series = "2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022",

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Zhou, H, Ye, B & Gai, W 2022, A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver. in 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022. 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022, Institute of Electrical and Electronics Engineers Inc., pp. 377-381, 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022, Xi'an, China, 28/10/22. https://doi.org/10.1109/ICICM56102.2022.10011239

A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver. / Zhou, Hang; Ye, Bingyi; Gai, Weixin.
2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 377-381 (2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.

AB - With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.

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KW - quadrature error canceller

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Zhou H, Ye B, Gai W. A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver. In 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 377-381. (2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022). doi: 10.1109/ICICM56102.2022.10011239

A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver

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