A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction

Geng Mu; Liangjian Lyu; Dawei Ye; C. J. Richard Shi

doi:10.1049/ell2.12774

A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction

Geng Mu, Liangjian Lyu, Dawei Ye, C. J. Richard Shi

School of Communication and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This letter presents a low-noise implementation of the switched-capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty-cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65-nm complementary metal-oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input-referred noise, integrated from 0.5 to 250 Hz, and 110-mV electrode-DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

Original language	English
Article number	e12774
Journal	Electronics Letters
Volume	59
Issue number	7
DOIs	https://doi.org/10.1049/ell2.12774
State	Published - Apr 2023

Keywords

choppers (circuits)
instrumentation amplifiers
switched-capacitor filters

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10.1049/ell2.12774

Cite this

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title = "A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction",

abstract = "This letter presents a low-noise implementation of the switched-capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty-cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65-nm complementary metal-oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input-referred noise, integrated from 0.5 to 250 Hz, and 110-mV electrode-DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.",

keywords = "choppers (circuits), instrumentation amplifiers, switched-capacitor filters",

author = "Geng Mu and Liangjian Lyu and Dawei Ye and \{Richard Shi\}, \{C. J.\}",

note = "Publisher Copyright: {\textcopyright} 2023 The Authors. Electronics Letters published by John Wiley \& Sons Ltd on behalf of The Institution of Engineering and Technology.",

year = "2023",

month = apr,

doi = "10.1049/ell2.12774",

language = "英语",

volume = "59",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley \& Sons Inc.",

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T1 - A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction

AU - Mu, Geng

AU - Lyu, Liangjian

AU - Ye, Dawei

AU - Richard Shi, C. J.

PY - 2023/4

Y1 - 2023/4

N2 - This letter presents a low-noise implementation of the switched-capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty-cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65-nm complementary metal-oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input-referred noise, integrated from 0.5 to 250 Hz, and 110-mV electrode-DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

AB - This letter presents a low-noise implementation of the switched-capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty-cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65-nm complementary metal-oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input-referred noise, integrated from 0.5 to 250 Hz, and 110-mV electrode-DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

KW - choppers (circuits)

KW - instrumentation amplifiers

KW - switched-capacitor filters

UR - https://www.scopus.com/pages/publications/85153352807

U2 - 10.1049/ell2.12774

DO - 10.1049/ell2.12774

M3 - 文章

AN - SCOPUS:85153352807

SN - 0013-5194

VL - 59

JO - Electronics Letters

JF - Electronics Letters

IS - 7

M1 - e12774

ER -

A chopper amplifier with a low duty-cycle sub-sampling in the switched-capacitor integrator for noise reduction

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