A Bandwidth-Tracking Self-Biased 5-To-2800 MHz Low-Jitter Clock Generator in 55nm CMOS

This paper presents a bandwidth-Tracking wideband and low-jitter clock generator (CLG) circuit designed in a 55 nm CMOS technology. Based on a self-biased phase-locked loop (PLL) structure, bias currents of the charge pump (CP), the voltage-controlled oscillator (VCO) and the differential-To-singled-ended (DTS) converter are synergetically generated and are designed to be proportionally scaled in accordance with the PLL output frequency. This allows the PLL loop bandwidth to track the input reference frequency for robust and stable operation. With the technique, the input reference frequency and the divider ratio of the PLL can also be jointly adjusted to optimize the PLL jitter performance. The CLG circuit covers a 5-To-2800 MHz frequency range while occupying a core area of 0.0621 mm² and dissipating 11.04 mW of power from 1.2 V power supply at 1 GHz output frequency. At 1 GHz, the PLL has a measured RMS jitter of 1.53 pS and a phase noise of-91.82 dBc/Hz at 1 MHz offset and-112.4 dBc/Hz at 10 MHz offset, respectively.