A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

Ying Dan Jiang; Run Xi Zhang; Chun Qi Shi; Zong Sheng Lai

doi:10.1007/s10470-012-9840-9

A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

Ying Dan Jiang, Run Xi Zhang, Chun Qi Shi, Zong Sheng Lai

School of Communication and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper presents a semi-active in-phase/quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13 μm CMOS technology. It features 5 dB conversion gain over a broad range from 800 MHz to 2.1 GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is +76 dBm at 2.1 GHz and suitable for application within a direct-conversion receiver.

Original language	English
Pages (from-to)	129-139
Number of pages	11
Journal	Analog Integrated Circuits and Signal Processing
Volume	72
Issue number	1
DOIs	https://doi.org/10.1007/s10470-012-9840-9
State	Published - Jul 2012

Keywords

CMOS radio frequency integrated circuit
Direct-conversion receiver
Input second-order intercept point
Quadrature
RFID
Semi-active mixer
TD-SCDMA

Access to Document

10.1007/s10470-012-9840-9

Cite this

@article{db50598b8eeb4a8aa900d455f67c515e,

title = "A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications",

abstract = "This paper presents a semi-active in-phase/quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13 μm CMOS technology. It features 5 dB conversion gain over a broad range from 800 MHz to 2.1 GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is +76 dBm at 2.1 GHz and suitable for application within a direct-conversion receiver.",

keywords = "CMOS radio frequency integrated circuit, Direct-conversion receiver, Input second-order intercept point, Quadrature, RFID, Semi-active mixer, TD-SCDMA",

author = "Jiang, \{Ying Dan\} and Zhang, \{Run Xi\} and Shi, \{Chun Qi\} and Lai, \{Zong Sheng\}",

year = "2012",

month = jul,

doi = "10.1007/s10470-012-9840-9",

language = "英语",

volume = "72",

pages = "129--139",

journal = "Analog Integrated Circuits and Signal Processing",

issn = "0925-1030",

publisher = "Springer Netherlands",

number = "1",

}

TY - JOUR

T1 - A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

AU - Jiang, Ying Dan

AU - Zhang, Run Xi

AU - Shi, Chun Qi

AU - Lai, Zong Sheng

PY - 2012/7

Y1 - 2012/7

N2 - This paper presents a semi-active in-phase/quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13 μm CMOS technology. It features 5 dB conversion gain over a broad range from 800 MHz to 2.1 GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is +76 dBm at 2.1 GHz and suitable for application within a direct-conversion receiver.

AB - This paper presents a semi-active in-phase/quadrature inductor-less down-conversion mixer. The mixer consists of an active trans-conductance stage, a passive current switching stage, and a trans-impedance stage. A complementary input architecture has been used to increase the trans-conductance for a given bias current. An on-chip prescaler is added to provide the balanced LO signals, while the CMFB circuit in trans-conductance stage is designed to enhance linearity. The chip was achieved in a 0.13 μm CMOS technology. It features 5 dB conversion gain over a broad range from 800 MHz to 2.1 GHz, which supports Chinese TD-SCDMA/RFID standards simultaneously. The maximum IIP2 is +76 dBm at 2.1 GHz and suitable for application within a direct-conversion receiver.

KW - CMOS radio frequency integrated circuit

KW - Direct-conversion receiver

KW - Input second-order intercept point

KW - Quadrature

KW - RFID

KW - Semi-active mixer

KW - TD-SCDMA

UR - https://www.scopus.com/pages/publications/84862803358

U2 - 10.1007/s10470-012-9840-9

DO - 10.1007/s10470-012-9840-9

M3 - 文章

AN - SCOPUS:84862803358

SN - 0925-1030

VL - 72

SP - 129

EP - 139

JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

IS - 1

ER -

A 76-dBm IIP2 down-conversion mixer for TD-SCDMA/RFID applications

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this