@inproceedings{7179270889674234a22df27c7190b9c5,
title = "A 71-86 GHz Cascaded Harmonic Enhanced Tripler with-69 dBc Fundamental and-66 dBc Second Harmonic Suppression",
abstract = "This paper proposed a cascaded harmonic enhanced injection-locked frequency tripler fabricated in a 40-nm CMOS process. In order to suppress the fundamental signal and the second harmonic signal, an injection-locked doubler is explored, and then the obtained ×2 frequency signal is mixed with the fundamental signal to realize the third harmonic signal and then the third harmonic signal is injected into the tank of the injection-locked frequency selection network to improve the output power. The tripler achieves a fundamental suppression over-69 dBc and a second harmonic suppression over-66 dBc. The output power over the entire locking range from 71.5 to 86.7 GHz is larger than 5.5 dBm. The chip occupies a die area of 0.25 × 0.35mm2 and dissipates 20 mW of power.",
keywords = "Frequency Tripler, Harmonic Enhancement, Harmonic Suppression, Injection-Locked",
author = "Zhaoqi Chen and Chunqi Shi and Yuri Lu and Runxi Zhang and Hao Deng and Jinghong Chen",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",
year = "2022",
doi = "10.1109/ISCAS48785.2022.9937280",
language = "英语",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "3347--3350",
booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2022",
address = "美国",
}