A 7 GHz, 1:2 CML Fanout Bu®er with Low Jitter and Skew

In this paper, the main source of jitter in current-mode logic (CML) buffer is analyzed in detail: thermal noise-induced jitter, flicker noise-induced jitter, and power supply-induced jitter. It is observed that big tail current or big tail transistor will reduce the impact of the jitter source, assuming a perfect power supply. Based on the principle above, a 7 GHz 1:2 CML fanout buffer with low additive jitter is proposed. A low additive RMS jitter of 46.39 fs, with integration from 12 kHz to 20 MHz, is achieved at a carrier frequency of 622 MHz. Typically, the maximum channel-channel skew, propagation delay, rise time, and fall time are 9.8 ps, 127 ps, 42.3 ps, and 38.6 ps, respectively. The proposed circuit dissipates 80 mA from a 3.3V supply voltage. Fabricated in 0.18 µm BiCOMS technology, the active area of the proposed buffer is 698 µm × 709 µm.