A 65 nm CMOS +14 dBm-Psat and 10%-PAE 81-86 GHz power amplifier with parallel combiner

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Abstract

This paper presents an 81-86 GHz E-band power amplifier fabricated with 65 nm CMOS process. A passive splitter is designed to transfer a pair of differential signal into two pairs of differential signals and satisfy phase requirement of output parallel power combiner. A substitution method is presented to trade off the simulation time and accuracy while using EM simulator to characterize the MOS transistor's access lines with stacked via arrays. The proposed PA achieves 9.5 dBm P1-dB, 14.16 dBm PSAT and 21.5 dB maximum power gain at 83.5 GHz. The PAEs at P1-dB and PSAT are 3.6% and 10.13% respectively.

Original languageEnglish
Title of host publication2015 Asia-Pacific Microwave Conference Proceedings, APMC 2015
EditorsFan Meng, Wei Hong, Guang-Qi Yang, Zhe Song, Xiao-Wei Zhu
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479987658
DOIs
StatePublished - 2015
Event2015 Asia-Pacific Microwave Conference, APMC 2015 - Nanjing, China
Duration: 6 Dec 20159 Dec 2015

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume3

Conference

Conference2015 Asia-Pacific Microwave Conference, APMC 2015
Country/TerritoryChina
CityNanjing
Period6/12/159/12/15

Keywords

  • Differential input
  • E-band
  • EM-simulation
  • parallel power amplifier
  • power splitter

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