TY - GEN
T1 - A 6-b 20-Gs/s 2-way time-interleaved flash ADC with automatic comparator offset calibration in 28-nm FDSOI
AU - Feng, Yulang
AU - Deng, Hao
AU - Fan, Qingjun
AU - Zhang, Runxi
AU - Bikkina, Phaneendra
AU - Chen, Jinghong
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020
Y1 - 2020
N2 - This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.
AB - This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.
KW - Back-gate voltage adjustment
KW - Comparator offset calibration
KW - FDSOI
KW - Flash ADC
KW - Time-interleaved ADC
UR - https://www.scopus.com/pages/publications/85092039543
M3 - 会议稿件
AN - SCOPUS:85092039543
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -