A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

Qingjun Fan; Runxi Zhang; Phaneendra Bikkina; Esko Mikkola; Jinghong Chen

doi:10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

Qingjun Fan^*
, Runxi Zhang
, Phaneendra Bikkina
, Esko Mikkola
, Jinghong Chen

^*Corresponding author for this work

School of Communication and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.

Original language	English
Title of host publication	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	193-196
Number of pages	4
ISBN (Electronic)	9781728115504
DOIs	https://doi.org/10.1109/ESSCIRC.2019.8902706
State	Published - Sep 2019
Event	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland Duration: 23 Sep 2019 → 26 Sep 2019

Publication series

Name	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Country/Territory	Poland
City	Cracow
Period	23/09/19 → 26/09/19

Access to Document

10.1109/ESSCIRC.2019.8902706

Cite this

Fan, Q., Zhang, R., Bikkina, P., Mikkola, E., & Chen, J. (2019). A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (pp. 193-196). Article 8902706 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902706

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title = "A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator",

abstract = "This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.",

author = "Qingjun Fan and Runxi Zhang and Phaneendra Bikkina and Esko Mikkola and Jinghong Chen",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",

year = "2019",

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doi = "10.1109/ESSCIRC.2019.8902706",

language = "英语",

series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

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booktitle = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

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Fan, Q, Zhang, R, Bikkina, P, Mikkola, E & Chen, J 2019, A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902706, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 193-196, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. / Fan, Qingjun; Zhang, Runxi; Bikkina, Phaneendra et al.
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 193-196 8902706 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.

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Fan Q, Zhang R, Bikkina P, Mikkola E, Chen J. A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 193-196. 8902706. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

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