@inproceedings{a58893eec13441769ad93b5dd2fafef7,
title = "A 4.7-mW 12-bit 100-MS/s Hybrid DAC",
abstract = "This paper presents a 12-bit digital-to-analog converter (DAC) with hybrid structure combining the current steering with the R-2R ladder structure, which can be used in low power applications demanding less than 100 MS/s conversion speed. It provides more than 85 dB spurious free dynamic range (SFDR) with 1 MHz output signal at 100 MHz sampling clock frequency. The achieved differential non-linearity (DNL) and integral non-linearity (INL) are equal to 0.91 and 0.81 LSB, respectively. The hybrid converter design is based on 55 nm CMOS technology and the overall system consumes 4.71 mW from 1.2 V digital (0.67 mW) and 2.5 V (4.04 mW) analog power supplies.",
author = "Wei Wang and Runxi Zhang and Chunqi Shi",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 ; Conference date: 31-10-2018 Through 03-11-2018",
year = "2018",
month = dec,
day = "5",
doi = "10.1109/ICSICT.2018.8565809",
language = "英语",
series = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Ting-Ao Tang and Fan Ye and Yu-Long Jiang",
booktitle = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",
address = "美国",
}