TY - GEN
T1 - A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
AU - Sheng, Kai
AU - Niu, Haowei
AU - Zhang, Boyang
AU - Gai, Weixin
AU - Ye, Bingyi
AU - Zhou, Hang
AU - Chen, Congcong
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Emerging bandwidth-hungry applications such as cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its excellent spectral efficiency. ADC-DSP-based coherent receivers [1]-[2] have been widely deployed in long-haul optical systems, but the high power consumption prohibits their application in power-sensitive short-reach links like 5G mobile backhaul networks, arousing eagerness for power-efficient analog solutions. An analog coherent receiver is proposed in [3], where a single-stage equalizer is used to compensate for chromatic dispersion (CD) and rotation of state of polarization (SOP), resulting in complex inter-connection, large parasitic capacitance, and consequently limited data rate. In this paper, we present a 200Gb/s analog dual-polarization quadrature phase-shift keying (DP-QPSK) coherent optical receiver featuring a 2-stage equalizer to relax the speed limit, while consuming 10 ×less power than ADC-DSP-based ones.
AB - Emerging bandwidth-hungry applications such as cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its excellent spectral efficiency. ADC-DSP-based coherent receivers [1]-[2] have been widely deployed in long-haul optical systems, but the high power consumption prohibits their application in power-sensitive short-reach links like 5G mobile backhaul networks, arousing eagerness for power-efficient analog solutions. An analog coherent receiver is proposed in [3], where a single-stage equalizer is used to compensate for chromatic dispersion (CD) and rotation of state of polarization (SOP), resulting in complex inter-connection, large parasitic capacitance, and consequently limited data rate. In this paper, we present a 200Gb/s analog dual-polarization quadrature phase-shift keying (DP-QPSK) coherent optical receiver featuring a 2-stage equalizer to relax the speed limit, while consuming 10 ×less power than ADC-DSP-based ones.
UR - https://www.scopus.com/pages/publications/85128284176
U2 - 10.1109/ISSCC42614.2022.9731797
DO - 10.1109/ISSCC42614.2022.9731797
M3 - 会议稿件
AN - SCOPUS:85128284176
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 282
EP - 284
BT - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Y2 - 20 February 2022 through 26 February 2022
ER -