A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm

Xiao Xiang; Wei Xin Gai; Ai He; Bing Yi Ye; Hao Wei Niu; Hang Zhou

doi:10.1109/ICSICT55466.2022.9963254

A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm

Xiao Xiang, Wei Xin Gai, Ai He, Bing Yi Ye, Hao Wei Niu, Hang Zhou

Peking University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a 40Gb/s PAM4 baud-rate clock and data recovery (CDR) with equal-slope (ES) algorithm. Comparing to MM-CDR, whether equipped with feedforward equalizer (FFE) on transmitter (TX) side or not, ES-CDR has advantages in recovered eye-height and timing margin by optimizing sampling point, while avoiding extra hardware cost. Realized in 28nm CMOS process, the ES-CDR showcases x7 orders of magnitude lower bit error rate (BER) for 12dB loss at 40Gb/s PAM4.

Original language	English
Title of host publication	Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
Editors	Fan Ye, Ting-Ao Tang
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665469067
DOIs	https://doi.org/10.1109/ICSICT55466.2022.9963254
State	Published - 2022
Externally published	Yes
Event	16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 - Nanjing, China Duration: 25 Oct 2022 → 28 Oct 2022

Publication series

Name	Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

Conference

Conference	16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
Country/Territory	China
City	Nanjing
Period	25/10/22 → 28/10/22

Access to Document

10.1109/ICSICT55466.2022.9963254

Cite this

Xiang, X., Gai, W. X., He, A., Ye, B. Y., Niu, H. W., & Zhou, H. (2022). A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm. In F. Ye, & T.-A. Tang (Eds.), Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 (Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT55466.2022.9963254

Xiang, Xiao ; Gai, Wei Xin ; He, Ai et al. / A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm. Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022. editor / Fan Ye ; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022).

@inproceedings{91a4495406da47ad9a0af381f853d459,

title = "A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm",

abstract = "This paper presents a 40Gb/s PAM4 baud-rate clock and data recovery (CDR) with equal-slope (ES) algorithm. Comparing to MM-CDR, whether equipped with feedforward equalizer (FFE) on transmitter (TX) side or not, ES-CDR has advantages in recovered eye-height and timing margin by optimizing sampling point, while avoiding extra hardware cost. Realized in 28nm CMOS process, the ES-CDR showcases x7 orders of magnitude lower bit error rate (BER) for 12dB loss at 40Gb/s PAM4.",

author = "Xiao Xiang and Gai, \{Wei Xin\} and Ai He and Ye, \{Bing Yi\} and Niu, \{Hao Wei\} and Hang Zhou",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022 ; Conference date: 25-10-2022 Through 28-10-2022",

year = "2022",

doi = "10.1109/ICSICT55466.2022.9963254",

language = "英语",

series = "Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Fan Ye and Ting-Ao Tang",

booktitle = "Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022",

address = "美国",

}

Xiang, X, Gai, WX, He, A, Ye, BY, Niu, HW & Zhou, H 2022, A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm. in F Ye & T-A Tang (eds), Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022. Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022, Institute of Electrical and Electronics Engineers Inc., 16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022, Nanjing, China, 25/10/22. https://doi.org/10.1109/ICSICT55466.2022.9963254

A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm. / Xiang, Xiao; Gai, Wei Xin; He, Ai et al.
Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022. ed. / Fan Ye; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm

AU - Xiang, Xiao

AU - Gai, Wei Xin

AU - He, Ai

AU - Ye, Bing Yi

AU - Niu, Hao Wei

AU - Zhou, Hang

PY - 2022

Y1 - 2022

N2 - This paper presents a 40Gb/s PAM4 baud-rate clock and data recovery (CDR) with equal-slope (ES) algorithm. Comparing to MM-CDR, whether equipped with feedforward equalizer (FFE) on transmitter (TX) side or not, ES-CDR has advantages in recovered eye-height and timing margin by optimizing sampling point, while avoiding extra hardware cost. Realized in 28nm CMOS process, the ES-CDR showcases x7 orders of magnitude lower bit error rate (BER) for 12dB loss at 40Gb/s PAM4.

AB - This paper presents a 40Gb/s PAM4 baud-rate clock and data recovery (CDR) with equal-slope (ES) algorithm. Comparing to MM-CDR, whether equipped with feedforward equalizer (FFE) on transmitter (TX) side or not, ES-CDR has advantages in recovered eye-height and timing margin by optimizing sampling point, while avoiding extra hardware cost. Realized in 28nm CMOS process, the ES-CDR showcases x7 orders of magnitude lower bit error rate (BER) for 12dB loss at 40Gb/s PAM4.

UR - https://www.scopus.com/pages/publications/85143976486

U2 - 10.1109/ICSICT55466.2022.9963254

DO - 10.1109/ICSICT55466.2022.9963254

M3 - 会议稿件

AN - SCOPUS:85143976486

T3 - Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

BT - Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

A2 - Ye, Fan

A2 - Tang, Ting-Ao

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

Y2 - 25 October 2022 through 28 October 2022

ER -

Xiang X, Gai WX, He A, Ye BY, Niu HW, Zhou H. A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm. In Ye F, Tang TA, editors, Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022. Institute of Electrical and Electronics Engineers Inc. 2022. (Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022). doi: 10.1109/ICSICT55466.2022.9963254

A 40Gb/s PAM4 Baud-Rate CDR with Equal-Slope Algorithm

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this