TY - GEN
T1 - A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC
AU - Deng, Hao
AU - Zhang, Runxi
AU - Chen, Jinghong
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents a successive-approximation register (SAR)-assisted two-step digital-slope analog-to-digital converter (ADC), which takes advantage of both the moderate conversion speed of the SAR ADC and the low noise characteristic of the digital-slope ADC. To improve the digital-slope ADC conversion speed while maintaining its power efficiency benefit, a novel architecture with a 5-bit SAR ADC as the coarse stage and a 6-bit two-step digital-slope ADC as the fine stage is proposed. A charge-sharing-based implementation of the twostep digital-slope ADC eliminates the need for power-consuming on-chip reference buffers and residue calibrations between the SAR and digital slope stages. Designed and simulated in a 55 nm CMOS technology, the proposed ADC achieves an SNDR of 56.27 dB at 400 MS/s while dissipating 2.4 mW, leading to a FOM of 11.24 fJ/conv.-step.
AB - This paper presents a successive-approximation register (SAR)-assisted two-step digital-slope analog-to-digital converter (ADC), which takes advantage of both the moderate conversion speed of the SAR ADC and the low noise characteristic of the digital-slope ADC. To improve the digital-slope ADC conversion speed while maintaining its power efficiency benefit, a novel architecture with a 5-bit SAR ADC as the coarse stage and a 6-bit two-step digital-slope ADC as the fine stage is proposed. A charge-sharing-based implementation of the twostep digital-slope ADC eliminates the need for power-consuming on-chip reference buffers and residue calibrations between the SAR and digital slope stages. Designed and simulated in a 55 nm CMOS technology, the proposed ADC achieves an SNDR of 56.27 dB at 400 MS/s while dissipating 2.4 mW, leading to a FOM of 11.24 fJ/conv.-step.
KW - Analog-to-digital converter (ADC)
KW - SAR ADC
KW - two-step digital-slope ADC
UR - https://www.scopus.com/pages/publications/85185376076
U2 - 10.1109/MWSCAS57524.2023.10405906
DO - 10.1109/MWSCAS57524.2023.10405906
M3 - 会议稿件
AN - SCOPUS:85185376076
T3 - Midwest Symposium on Circuits and Systems
SP - 987
EP - 990
BT - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Y2 - 6 August 2023 through 9 August 2023
ER -