TY - GEN
T1 - A 400 MHz, 8-bit, 1.75-ps resolution pipelined-two-step time-to-digital converter with dynamic time amplification
AU - Tu, Yuting
AU - Xu, Rongjin
AU - Ye, Dawei
AU - Lyu, Liangjian
AU - Shi, C. J.Richard
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020
Y1 - 2020
N2 - This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplification (DTA) to improve the resolution at low power. The key element of this TDC is the DTA. It samples the residual time errors as voltages held in the MOM capacitors and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA realizes high linearity and power efficiency, and can be employed to build a pipeline TDC architecture with high sampling frequency because of its sample and hold operation. Moreover, the DTA maintains constant gain, so only a one-time forground calibration for gain mismatch is required in this TDC. Simulations show that the TDC designed in 65 nm CMOS achieves 8-bit, 1.75 ps of time resolution, and 1 LSB INL and 1.6 LSB DNL with one-time foreground calibration at 400 MHz sampling frequency while just consuming 726 μW power, which corresponds to 18.45 fJ/Conv. FoM.
AB - This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplification (DTA) to improve the resolution at low power. The key element of this TDC is the DTA. It samples the residual time errors as voltages held in the MOM capacitors and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA realizes high linearity and power efficiency, and can be employed to build a pipeline TDC architecture with high sampling frequency because of its sample and hold operation. Moreover, the DTA maintains constant gain, so only a one-time forground calibration for gain mismatch is required in this TDC. Simulations show that the TDC designed in 65 nm CMOS achieves 8-bit, 1.75 ps of time resolution, and 1 LSB INL and 1.6 LSB DNL with one-time foreground calibration at 400 MHz sampling frequency while just consuming 726 μW power, which corresponds to 18.45 fJ/Conv. FoM.
KW - Phase-locked loop(PLL)
KW - Time amplifier(TA)
KW - Time-to-digital converter (TDC)
KW - Time-to-voltage converter (TVC)
KW - Two-step architecture
KW - Voltage-to-time converter (VTC)
UR - https://www.scopus.com/pages/publications/85109315991
M3 - 会议稿件
AN - SCOPUS:85109315991
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -