@inproceedings{06e35c4079fc48f4b903c45aff7d882a,
title = "A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros",
abstract = "Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of 2.53 μW/channel and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5\% in a 32-channel scenario.",
keywords = "adaptive threshold, computing-in-memory, event-driven, low power, on-chip learning, sparsity, spike sorting, template matching",
author = "Hao Jiang and Jiapei Zheng and Yunzhengmao Wang and Jinshan Zhang and Haozhe Zhu and Liangjian Lyu and Yingping Chen and Chixiao Chen and Qi Liu",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",
year = "2023",
doi = "10.1109/ISCAS46773.2023.10181615",
language = "英语",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings",
address = "美国",
}
