A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Hao Jiang; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu

doi:10.1109/ISCAS46773.2023.10181615

A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Hao Jiang
, Jiapei Zheng
, Yunzhengmao Wang
, Jinshan Zhang
, Haozhe Zhu
, Liangjian Lyu
, Yingping Chen
, Chixiao Chen
, Qi Liu

School of Communication and Electronic Engineering

Fudan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of 2.53 μW/channel and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

Original language	English
Title of host publication	ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665451093
DOIs	https://doi.org/10.1109/ISCAS46773.2023.10181615
State	Published - 2023
Event	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States Duration: 21 May 2023 → 25 May 2023

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2023-May
ISSN (Print)	0271-4310

Conference

Conference	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/Territory	United States
City	Monterey
Period	21/05/23 → 25/05/23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

adaptive threshold
computing-in-memory
event-driven
low power
on-chip learning
sparsity
spike sorting
template matching

Access to Document

10.1109/ISCAS46773.2023.10181615

Cite this

Jiang, H., Zheng, J., Wang, Y., Zhang, J., Zhu, H., Lyu, L., Chen, Y., Chen, C., & Liu, Q. (2023). A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. In ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2023-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS46773.2023.10181615

Jiang, Hao ; Zheng, Jiapei ; Wang, Yunzhengmao et al. / A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{06e35c4079fc48f4b903c45aff7d882a,

title = "A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros",

abstract = "Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of 2.53 μW/channel and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5\% in a 32-channel scenario.",

keywords = "adaptive threshold, computing-in-memory, event-driven, low power, on-chip learning, sparsity, spike sorting, template matching",

author = "Hao Jiang and Jiapei Zheng and Yunzhengmao Wang and Jinshan Zhang and Haozhe Zhu and Liangjian Lyu and Yingping Chen and Chixiao Chen and Qi Liu",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",

year = "2023",

doi = "10.1109/ISCAS46773.2023.10181615",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings",

address = "美国",

}

Jiang, H, Zheng, J, Wang, Y, Zhang, J, Zhu, H, Lyu, L, Chen, Y, Chen, C & Liu, Q 2023, A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. in ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2023-May, Institute of Electrical and Electronics Engineers Inc., 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, United States, 21/05/23. https://doi.org/10.1109/ISCAS46773.2023.10181615

A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. / Jiang, Hao; Zheng, Jiapei; Wang, Yunzhengmao et al.
ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2023-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

AU - Jiang, Hao

AU - Zheng, Jiapei

AU - Wang, Yunzhengmao

AU - Zhang, Jinshan

AU - Zhu, Haozhe

AU - Lyu, Liangjian

AU - Chen, Yingping

AU - Chen, Chixiao

AU - Liu, Qi

PY - 2023

Y1 - 2023

N2 - Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of 2.53 μW/channel and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

AB - Spike sorting processors with high energy efficiency are widely used in large-scale neural signal processing tasks to monitor the activity of neurons in brains. This paper presents a low-power processor for high-accuracy spike sorting and on-chip incremental learning using an algorithm-hardware co-design approach. The processor introduces an event-driven mechanism with adaptive-threshold detection to conditionally activate the system in order to reduce power consumption. Sparsity-aware computing-in-memory (CIM) macros are also developed in our design to store templates and perform complicated computations efficiently. The prototype is designed using 28nm technology with an area of 0.018 mm2/channel and an overall power efficiency of 2.53 μW/channel and 84nW/(channel.cluster) at the voltage of 0.72V. Moreover, the accuracy of the whole design can reach 94.5% in a 32-channel scenario.

KW - adaptive threshold

KW - computing-in-memory

KW - event-driven

KW - low power

KW - on-chip learning

KW - sparsity

KW - spike sorting

KW - template matching

UR - https://www.scopus.com/pages/publications/85167685780

U2 - 10.1109/ISCAS46773.2023.10181615

DO - 10.1109/ISCAS46773.2023.10181615

M3 - 会议稿件

AN - SCOPUS:85167685780

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023

Y2 - 21 May 2023 through 25 May 2023

ER -

Jiang H, Zheng J, Wang Y, Zhang J, Zhu H, Lyu L et al. A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. In ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS46773.2023.10181615

A 2.53 μW/channel Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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