TY - GEN
T1 - A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
AU - Ye, Bingyi
AU - Sheng, Kai
AU - Gai, Weixin
AU - Niu, Haowei
AU - Zhang, Boyang
AU - He, Yandong
AU - Jia, Song
AU - Chen, Congcong
AU - Yu, Jiaqi
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1st-tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3, 4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.
AB - The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1st-tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3, 4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.
UR - https://www.scopus.com/pages/publications/85128316432
U2 - 10.1109/ISSCC42614.2022.9731591
DO - 10.1109/ISSCC42614.2022.9731591
M3 - 会议稿件
AN - SCOPUS:85128316432
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 118
EP - 120
BT - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Y2 - 20 February 2022 through 26 February 2022
ER -
