A 21.3–24.5 Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

This paper presents a 21.3–24.5 Gb/s phase locked loop (PLL)based reference-less clock and data recovery (CDR) circuit. A cascode-coupled technique is used in the design of the quadrature voltage-controlled oscillator (VCO), which eliminates the phenomenon of dual-mode oscillation, provides a stable phase sequence for frequency acquisition and ensures the correct loop locking. The dual loop topology is adopted to realize a wide frequency acquisition range and an autonomous transition from frequency locking to phase locking, while the PLL-based structure brings in an excellent jitter performance. When the data rate of the input PRBS9 is 24.5 Gb/s, the measured peak-to-peak jitter and the root-mean-square (RMS) jitter of the recovered clock are 2.7 ps and 0.39 ps respectively, and the peak-to-peak jitter and the RMS jitter of the recovered data are 7.7 ps and 1.5 ps respectively. Implemented in 55-nm CMOS technology, the CDR circuit occupies a core area of 0.7 mm² and consumes 170 mW at 1.2 V power supply.