A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work demonstrates a 200-Gb/s PAM-4 transmitter with 1.6-Vppd output swing in 12-nm FinFET technology. Novel pulse generators are proposed to reduce jitter by two orders of magnitude. The quadrature clock generator is capable of detecting and correcting three types of clock skews including duty-cycle error, quadrature error, and differential error. The power efficiency of the transmitter is 3.32 pJ/bit and the active area is 0.116

Original languageEnglish
Title of host publication2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350361469
DOIs
StatePublished - 2024
Externally publishedYes
Event2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States
Duration: 16 Jun 202420 Jun 2024

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/TerritoryUnited States
CityHonolulu
Period16/06/2420/06/24

Keywords

  • FinFET
  • Serdes
  • high-swing transmitter
  • quadrature clock generator

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