A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction

Rongjin Xu; Dawei Ye; Liangjian Lyu; C. J. Richard Shi

doi:10.1109/RFIC49505.2020.9218274

A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction

Rongjin Xu
, Dawei Ye^*
, Liangjian Lyu
, C. J. Richard Shi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to-55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.

Original language	English
Title of host publication	RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	11-14
Number of pages	4
ISBN (Electronic)	9781728168098
DOIs	https://doi.org/10.1109/RFIC49505.2020.9218274
State	Published - Aug 2020
Externally published	Yes
Event	2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 - Virtual, Los Angeles, United States Duration: 4 Aug 2020 → 6 Aug 2020

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume	2020-August
ISSN (Print)	1529-2517

Conference

Conference	2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020
Country/Territory	United States
City	Virtual, Los Angeles
Period	4/08/20 → 6/08/20

Keywords

clock multiplier
digital-controlled delay line (DCDL)
frequency tracking loop (FTL)
injection-locked
ring oscillator (RO)

Access to Document

10.1109/RFIC49505.2020.9218274

Cite this

Xu, R., Ye, D., Lyu, L., & Richard Shi, C. J. (2020). A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction. In RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium (pp. 11-14). Article 9218274 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2020-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC49505.2020.9218274

Xu, Rongjin ; Ye, Dawei ; Lyu, Liangjian et al. / A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction. RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 11-14 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

@inproceedings{48d06a2cd92246da99359fbd6ac0d6bb,

title = "A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction",

abstract = "This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to-55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.",

keywords = "clock multiplier, digital-controlled delay line (DCDL), frequency tracking loop (FTL), injection-locked, ring oscillator (RO)",

author = "Rongjin Xu and Dawei Ye and Liangjian Lyu and \{Richard Shi\}, \{C. J.\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 ; Conference date: 04-08-2020 Through 06-08-2020",

year = "2020",

month = aug,

doi = "10.1109/RFIC49505.2020.9218274",

language = "英语",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "11--14",

booktitle = "RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium",

address = "美国",

}

Xu, R, Ye, D, Lyu, L & Richard Shi, CJ 2020, A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction. in RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium., 9218274, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol. 2020-August, Institute of Electrical and Electronics Engineers Inc., pp. 11-14, 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020, Virtual, Los Angeles, United States, 4/08/20. https://doi.org/10.1109/RFIC49505.2020.9218274

A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction. / Xu, Rongjin; Ye, Dawei; Lyu, Liangjian et al.
RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium. Institute of Electrical and Electronics Engineers Inc., 2020. p. 11-14 9218274 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2020-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction

AU - Xu, Rongjin

AU - Ye, Dawei

AU - Lyu, Liangjian

AU - Richard Shi, C. J.

PY - 2020/8

Y1 - 2020/8

N2 - This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to-55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.

AB - This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to-55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.

KW - clock multiplier

KW - digital-controlled delay line (DCDL)

KW - frequency tracking loop (FTL)

KW - injection-locked

KW - ring oscillator (RO)

UR - https://www.scopus.com/pages/publications/85093941597

U2 - 10.1109/RFIC49505.2020.9218274

DO - 10.1109/RFIC49505.2020.9218274

M3 - 会议稿件

AN - SCOPUS:85093941597

T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

SP - 11

EP - 14

BT - RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020

Y2 - 4 August 2020 through 6 August 2020

ER -

Xu R, Ye D, Lyu L, Richard Shi CJ. A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction. In RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium. Institute of Electrical and Electronics Engineers Inc. 2020. p. 11-14. 9218274. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC49505.2020.9218274

A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction

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Keywords

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