A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling

Jiaqing Rui; Liangjian Lyu; Yuting Wan; Kexin Shan; Wenxian Gu; C. J.Richard Shi; Xing Wu

doi:10.1109/ISSCC49663.2026.11409143

A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling

Jiaqing Rui
, Liangjian Lyu^*
, Yuting Wan
, Kexin Shan
, Wenxian Gu
, C. J.Richard Shi
, Xing Wu

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University
University of Washington

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a process-independent, curvature-compensated bandgap reference. By introducing a temperature-adaptive duty-cycled resistor to scale the PTAT voltage, the design effectively compensates for CTAT nonlinearity without introducing offset errors. Fabricated in 0.18μm CMOS, the prototype chip occupies 0.068mm² and consumes 15μA. After two-point trimming, it achieves an average temperature coefficient of 1ppm/°C and a 3σ output accuracy within ±0.066%.

Original language	English
Title of host publication	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	84-86
Number of pages	3
ISBN (Electronic)	9798331589363
DOIs	https://doi.org/10.1109/ISSCC49663.2026.11409143
State	Published - 2026
Event	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 - San Francisco, United States Duration: 15 Feb 2026 → 19 Feb 2026

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	69
ISSN (Print)	0193-6530

Conference

Conference	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
Country/Territory	United States
City	San Francisco
Period	15/02/26 → 19/02/26

Access to Document

10.1109/ISSCC49663.2026.11409143

Cite this

Rui, J., Lyu, L., Wan, Y., Shan, K., Gu, W., Shi, C. J. R., & Wu, X. (2026). A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling. In 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 (pp. 84-86). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 69). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC49663.2026.11409143

Rui, Jiaqing ; Lyu, Liangjian ; Wan, Yuting et al. / A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling. 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc., 2026. pp. 84-86 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{50fc8a7ee7ae4ed485188dce029af42c,

title = "A 1ppm/°C and ±0.066\% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling",

abstract = "This paper presents a process-independent, curvature-compensated bandgap reference. By introducing a temperature-adaptive duty-cycled resistor to scale the PTAT voltage, the design effectively compensates for CTAT nonlinearity without introducing offset errors. Fabricated in 0.18μm CMOS, the prototype chip occupies 0.068mm2 and consumes 15μA. After two-point trimming, it achieves an average temperature coefficient of 1ppm/°C and a 3σ output accuracy within ±0.066\%.",

author = "Jiaqing Rui and Liangjian Lyu and Yuting Wan and Kexin Shan and Wenxian Gu and Shi, \{C. J.Richard\} and Xing Wu",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 ; Conference date: 15-02-2026 Through 19-02-2026",

year = "2026",

doi = "10.1109/ISSCC49663.2026.11409143",

language = "英语",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "84--86",

booktitle = "2026 IEEE International Solid-State Circuits Conference, ISSCC 2026",

address = "美国",

}

Rui, J, Lyu, L, Wan, Y, Shan, K, Gu, W, Shi, CJR & Wu, X 2026, A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling. in 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 69, Institute of Electrical and Electronics Engineers Inc., pp. 84-86, 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, United States, 15/02/26. https://doi.org/10.1109/ISSCC49663.2026.11409143

A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling. / Rui, Jiaqing; Lyu, Liangjian; Wan, Yuting et al.
2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc., 2026. p. 84-86 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 69).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling

AU - Rui, Jiaqing

AU - Lyu, Liangjian

AU - Wan, Yuting

AU - Shan, Kexin

AU - Gu, Wenxian

AU - Shi, C. J.Richard

AU - Wu, Xing

PY - 2026

Y1 - 2026

N2 - This paper presents a process-independent, curvature-compensated bandgap reference. By introducing a temperature-adaptive duty-cycled resistor to scale the PTAT voltage, the design effectively compensates for CTAT nonlinearity without introducing offset errors. Fabricated in 0.18μm CMOS, the prototype chip occupies 0.068mm2 and consumes 15μA. After two-point trimming, it achieves an average temperature coefficient of 1ppm/°C and a 3σ output accuracy within ±0.066%.

AB - This paper presents a process-independent, curvature-compensated bandgap reference. By introducing a temperature-adaptive duty-cycled resistor to scale the PTAT voltage, the design effectively compensates for CTAT nonlinearity without introducing offset errors. Fabricated in 0.18μm CMOS, the prototype chip occupies 0.068mm2 and consumes 15μA. After two-point trimming, it achieves an average temperature coefficient of 1ppm/°C and a 3σ output accuracy within ±0.066%.

UR - https://www.scopus.com/pages/publications/105035322379

U2 - 10.1109/ISSCC49663.2026.11409143

DO - 10.1109/ISSCC49663.2026.11409143

M3 - 会议稿件

AN - SCOPUS:105035322379

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 84

EP - 86

BT - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026

Y2 - 15 February 2026 through 19 February 2026

ER -

Rui J, Lyu L, Wan Y, Shan K, Gu W, Shi CJR et al. A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling. In 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc. 2026. p. 84-86. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC49663.2026.11409143

A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling

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