TY - GEN
T1 - A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications
AU - Liu, Zheyu
AU - Ren, Erxiang
AU - Luo, Li
AU - Wei, Qi
AU - Wu, Xing
AU - Li, Xueqing
AU - Qiao, Fei
AU - Liu, Xin Jun
AU - Yang, Huazhong
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.
AB - In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.
KW - Artificial Intelligence
KW - Low power
KW - Near-sensor processing
KW - Smart sensor
UR - https://www.scopus.com/pages/publications/85072976185
U2 - 10.1109/ISVLSI.2019.00087
DO - 10.1109/ISVLSI.2019.00087
M3 - 会议稿件
AN - SCOPUS:85072976185
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 447
EP - 452
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Y2 - 15 July 2019 through 17 July 2019
ER -
