A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications

Zheyu Liu; Erxiang Ren; Li Luo; Qi Wei; Xing Wu; Xueqing Li; Fei Qiao; Xin Jun Liu; Huazhong Yang

doi:10.1109/ISVLSI.2019.00087

A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications

Zheyu Liu
, Erxiang Ren
, Li Luo
, Qi Wei
, Xing Wu
, Xueqing Li
, Fei Qiao^*
, Xin Jun Liu
, Huazhong Yang

^*Corresponding author for this work

School of Communication and Electronic Engineering

Tsinghua University
Beijing Jiaotong University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Publisher	IEEE Computer Society
Pages	447-452
Number of pages	6
ISBN (Electronic)	9781538670996
DOIs	https://doi.org/10.1109/ISVLSI.2019.00087
State	Published - Jul 2019
Event	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States Duration: 15 Jul 2019 → 17 Jul 2019

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2019-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Country/Territory	United States
City	Miami
Period	15/07/19 → 17/07/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Artificial Intelligence
Low power
Near-sensor processing
Smart sensor

Access to Document

10.1109/ISVLSI.2019.00087

Cite this

Liu, Z., Ren, E., Luo, L., Wei, Q., Wu, X., Li, X., Qiao, F., Liu, X. J., & Yang, H. (2019). A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 447-452). Article 8839347 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2019.00087

@inproceedings{10abe7fec8e14eff99ff2f3a668abdc1,

title = "A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications",

abstract = "In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.",

keywords = "Artificial Intelligence, Low power, Near-sensor processing, Smart sensor",

author = "Zheyu Liu and Erxiang Ren and Li Luo and Qi Wei and Xing Wu and Xueqing Li and Fei Qiao and Liu, \{Xin Jun\} and Huazhong Yang",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 ; Conference date: 15-07-2019 Through 17-07-2019",

year = "2019",

month = jul,

doi = "10.1109/ISVLSI.2019.00087",

language = "英语",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

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Liu, Z, Ren, E, Luo, L, Wei, Q, Wu, X, Li, X, Qiao, F, Liu, XJ & Yang, H 2019, A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. in Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019., 8839347, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2019-July, IEEE Computer Society, pp. 447-452, 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, United States, 15/07/19. https://doi.org/10.1109/ISVLSI.2019.00087

A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. / Liu, Zheyu; Ren, Erxiang; Luo, Li et al.
Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, 2019. p. 447-452 8839347 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ren, Erxiang

AU - Luo, Li

AU - Wei, Qi

AU - Wu, Xing

AU - Li, Xueqing

AU - Qiao, Fei

AU - Liu, Xin Jun

AU - Yang, Huazhong

PY - 2019/7

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AB - In the past few years, the demand for intelligence of IoT front-end devices has dramatically increased. However, such devices face challenges of limited on-chip resources and strict power or energy constraints. Recent progress in binarized neural networks has provided promising solutions for front-end processing system to conduct simple detection and classification tasks by making trade-offs between the processing quality and the computation complexity. In this paper, we propose a mixed-signal perception chip, in which an ADC-free 32x32 image sensor and a BNN processing array are directly integrated with a 180nm standard CMOS process. Taking advantage of the ADC-free processing architecture, the whole processing system only consumes 1.8mW power, while providing up to 545.4 GOPS/W energy efficiency. The implementation performance and energy efficiency are comparable with the state-of-the-art designs in much more advanced CMOS technologies. This work provides a promising alternative for low-power IoT intelligent applications.

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ER -

Liu Z, Ren E, Luo L, Wei Q, Wu X, Li X et al. A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society. 2019. p. 447-452. 8839347. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI.2019.00087

A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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