A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS

Bingyi Ye; Tianchen Ye; Tianyuan Zhong; Zhiwen Huang; Lei Shen; Boyang Zhang; Dunshan Yu; Yandong He; Weixin Gai

doi:10.1109/ISSCC49661.2025.10904800

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS

Bingyi Ye
, Tianchen Ye
, Tianyuan Zhong
, Zhiwen Huang
, Lei Shen
, Boyang Zhang
, Dunshan Yu
, Yandong He
, Weixin Gai

School of Communication and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1]-[3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuous time linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4]-[5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock generator (CG).

Original language	English
Title of host publication	2025 IEEE International Solid-State Circuits Conference, ISSCC 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	140-142
Number of pages	3
ISBN (Electronic)	9798331541019
DOIs	https://doi.org/10.1109/ISSCC49661.2025.10904800
State	Published - 2025
Event	72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francisco, United States Duration: 16 Feb 2025 → 20 Feb 2025

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	72nd IEEE International Solid-State Circuits Conference, ISSCC 2025
Country/Territory	United States
City	San Francisco
Period	16/02/25 → 20/02/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISSCC49661.2025.10904800

Cite this

Ye, B., Ye, T., Zhong, T., Huang, Z., Shen, L., Zhang, B., Yu, D., He, Y., & Gai, W. (2025). A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. In 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025 (pp. 140-142). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC49661.2025.10904800

Ye, Bingyi ; Ye, Tianchen ; Zhong, Tianyuan et al. / A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. pp. 140-142 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS",

abstract = "Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1]-[3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuous time linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4]-[5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock generator (CG).",

author = "Bingyi Ye and Tianchen Ye and Tianyuan Zhong and Zhiwen Huang and Lei Shen and Boyang Zhang and Dunshan Yu and Yandong He and Weixin Gai",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 ; Conference date: 16-02-2025 Through 20-02-2025",

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doi = "10.1109/ISSCC49661.2025.10904800",

language = "英语",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Ye, B, Ye, T, Zhong, T, Huang, Z, Shen, L, Zhang, B, Yu, D, He, Y & Gai, W 2025, A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. in 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 140-142, 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, United States, 16/02/25. https://doi.org/10.1109/ISSCC49661.2025.10904800

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. / Ye, Bingyi; Ye, Tianchen; Zhong, Tianyuan et al.
2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. p. 140-142 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS

AU - Ye, Bingyi

AU - Ye, Tianchen

AU - Zhong, Tianyuan

AU - Huang, Zhiwen

AU - Shen, Lei

AU - Zhang, Boyang

AU - Yu, Dunshan

AU - He, Yandong

AU - Gai, Weixin

PY - 2025

Y1 - 2025

N2 - Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1]-[3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuous time linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4]-[5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock generator (CG).

AB - Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1]-[3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuous time linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4]-[5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock generator (CG).

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BT - 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 16 February 2025 through 20 February 2025

ER -

Ye B, Ye T, Zhong T, Huang Z, Shen L, Zhang B et al. A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. In 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc. 2025. p. 140-142. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC49661.2025.10904800

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS

Abstract

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UN SDGs

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