A 103 fs RMS jitter calibration-free gain-boosting quadrature oversampling PLL utilizing an isolated reference sampling phase detector

Yixian Li, Chunqi Shi, Jinghong Chen, Runxi Zhang

Research output: Contribution to journalArticlepeer-review

Abstract

This letter presents an integer-N quadrature oversampling phase-locked loop (QOPLL) operating at 5.76–6.48 GHz with low RMS jitter. The QOPLL features a calibration-free gain-boosting quadrature oversampling mechanism. The proposed gain-boosting quadrature over sampling mechanism addresses the incompatibility issues in conventional oversampling mechanisms and gain-boosting techniques. It enhances in band phase noise performance while eliminating the need for phase detector gain calibration. An isolated reference sampling phase detector (IRSPD) has been developed to ensure quadrature phase accuracy and improve phase detector gain. The QOPLL is fabricated in a 40-nm CMOS process. Measurement results demonstrate an RMS jitter of 103 fs, integrated from 10 kHz to 100 MHz. The reference spur is −71.26 dBc. The power consumption is 15 mW.

Original languageEnglish
JournalIEICE Electronics Express
Volume22
Issue number13
DOIs
StatePublished - 2025

Keywords

  • Integrated circuits
  • gain-boosting
  • low jitter
  • oversampling PLL
  • phase detector

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