A 10 Gb/s PAM4 receiver with reference-less half-rate Bang-Bang CDR in 180-nm CMOS

This paper discusses a 10 Gb/s PAM4 wireline receiver that employs bandwidth compensation in analog front-end (AFE), high performance half rate data recovery circuit and clock recovery circuit without reference clock. The combination of continuous-time linear equalizer (CTLE) with peaking inductance and transimpedance amplifier (TIA) based on inverter improves the bandwidth and gain of AFE. Level shifter and limiting amplifier (LA) achieve the conversion of multi-level signals to thermometer codes and reduces the accuracy or adaptive requirements of comparator threshold voltage. The jitter of clock recovery circuit is effectively reduced by the half rate Bang-Bang phase detector (BBPD), and quadrature LC-voltage-controlled oscillator (LC-VCO) guarantees the low jitter of recovered clock. The post-simulation results show that the receiver can provide as much as 6.086 dB equalization. The core of the receiver occupies 1.25 × 0.84 mm² area and consumes 195.42 mW power at the supply voltage of 1.8 V. The horizontal opening degree of recovered 2.5 Gb/s data reaches 0.8 UI and the jitter of recovered 2.5 Gb/s clock is 11.76 ps.