TY - GEN
T1 - A 0.473 μj/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction
AU - Gu, Wenxian
AU - Hao, Xudong
AU - Bi, Hengchang
AU - Wu, Xing
AU - Shi, C. J.Richard
AU - Lyu, Liangjian
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The closed-loop deep brain stimulation system demands high-performance seizure detection, especially in terms of ultra-low power consumption and patient specificity. In this paper, we propose a seizure detection approach featuring low-pass filters for feature extraction and a programmable linear support vector machine for classification. This approach effectively reduces power consumption while retaining the signal energy near the cutoff frequencies and preserving the correlation between adjacent frequency bands. To reduce the false alarm rate, a Hidden Markov Model is utilized for post-processing. The proposed processor also employed calculation bit-width optimization and time-division multiplexing to minimize power and area consumption, while maintaining minimal accuracy loss. Implemented in a 65-nm CMOS process, the processor occupies an active area of 0.14 mm2. It achieves an energy classification efficiency of 0.473 μJ/class with 0.7-V supply and 16.384-kHz system clock. The measurement results show a sensitivity of 95.92%, a specificity of 98.11%, and a false alarm rate of 1.78 times/h, as validated by the CHB-MIT dataset.
AB - The closed-loop deep brain stimulation system demands high-performance seizure detection, especially in terms of ultra-low power consumption and patient specificity. In this paper, we propose a seizure detection approach featuring low-pass filters for feature extraction and a programmable linear support vector machine for classification. This approach effectively reduces power consumption while retaining the signal energy near the cutoff frequencies and preserving the correlation between adjacent frequency bands. To reduce the false alarm rate, a Hidden Markov Model is utilized for post-processing. The proposed processor also employed calculation bit-width optimization and time-division multiplexing to minimize power and area consumption, while maintaining minimal accuracy loss. Implemented in a 65-nm CMOS process, the processor occupies an active area of 0.14 mm2. It achieves an energy classification efficiency of 0.473 μJ/class with 0.7-V supply and 16.384-kHz system clock. The measurement results show a sensitivity of 95.92%, a specificity of 98.11%, and a false alarm rate of 1.78 times/h, as validated by the CHB-MIT dataset.
KW - electroencephalogram
KW - frequency band feature extraction
KW - hidden markov model
KW - seizure detection
KW - support vector machine
UR - https://www.scopus.com/pages/publications/105010613447
U2 - 10.1109/ISCAS56072.2025.11043784
DO - 10.1109/ISCAS56072.2025.11043784
M3 - 会议稿件
AN - SCOPUS:105010613447
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Y2 - 25 May 2025 through 28 May 2025
ER -