A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

Yuxin Ji; Yuhang Zhang; Changyan Chen; Jian Zhao; Fakhrul Zaman Rokhani; Yehea Ismail; Yongfu Li

doi:10.1109/TVLSI.2024.3453946

A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

Yuxin Ji, Yuhang Zhang, Changyan Chen, Jian Zhao, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li

Research output: Contribution to journal › Article › peer-review

Abstract

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4× - 3.8× less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2× - 4×less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

Original language	English
Pages (from-to)	573-577
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	33
Issue number	2
DOIs	https://doi.org/10.1109/TVLSI.2024.3453946
State	Published - 2025
Externally published	Yes

Keywords

Data/state retention
flip-flop
ultralow power

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10.1109/TVLSI.2024.3453946

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title = "A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI",

abstract = "Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4× - 3.8× less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2× - 4×less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).",

keywords = "Data/state retention, flip-flop, ultralow power",

author = "Yuxin Ji and Yuhang Zhang and Changyan Chen and Jian Zhao and \{Zaman Rokhani\}, Fakhrul and Yehea Ismail and Yongfu Li",

note = "Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

year = "2025",

doi = "10.1109/TVLSI.2024.3453946",

language = "英语",

volume = "33",

pages = "573--577",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

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T1 - A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

AU - Ji, Yuxin

AU - Zhang, Yuhang

AU - Chen, Changyan

AU - Zhao, Jian

AU - Zaman Rokhani, Fakhrul

AU - Ismail, Yehea

AU - Li, Yongfu

PY - 2025

Y1 - 2025

N2 - Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4× - 3.8× less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2× - 4×less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

AB - Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4× - 3.8× less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2× - 4×less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

KW - Data/state retention

KW - flip-flop

KW - ultralow power

UR - https://www.scopus.com/pages/publications/85204872303

U2 - 10.1109/TVLSI.2024.3453946

DO - 10.1109/TVLSI.2024.3453946

M3 - 文章

AN - SCOPUS:85204872303

SN - 1063-8210

VL - 33

SP - 573

EP - 577

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 2

ER -

A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

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Keywords

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