6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

Bingyi Ye; Guangdong Wu; Weixin Gai; Kai Sheng; Yandong He

doi:10.1109/ISSCC42615.2023.10067348

6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

Bingyi Ye
, Guangdong Wu
, Weixin Gai
, Kai Sheng
, Yandong He

Peking University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time feed-forward equalizers (FFEs) in receivers (RXs) break the timing loop and compensate for electrical and optical impairments [2-3]. However, it relies on accurate, multiphase, and high-speed sampling clocks. The RX FFEs implemented in the continuous-time domain use active [4-5] or passive [5-6] delay lines, which eliminate clock and interleaved sample-and-hold circuits. In addition, the continuous-time FFE preserves edge information and therefore supports the oversampling clock and data recovery (CDR). This paper presents a 5-tap delay-line-based receiver FFE operating at 200Gb/s and equalizing a 17.2dB-loss channel.

Original language	English
Title of host publication	2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	112-114
Number of pages	3
ISBN (Electronic)	9781665428002
DOIs	https://doi.org/10.1109/ISSCC42615.2023.10067348
State	Published - 2023
Externally published	Yes
Event	2023 IEEE International Solid-State Circuits Conference, ISSCC 2023 - Virtual, Online, United States Duration: 19 Feb 2023 → 23 Feb 2023

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2023-February
ISSN (Print)	0193-6530

Conference

Conference	2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
Country/Territory	United States
City	Virtual, Online
Period	19/02/23 → 23/02/23

Access to Document

10.1109/ISSCC42615.2023.10067348

Cite this

Ye, B., Wu, G., Gai, W., Sheng, K., & He, Y. (2023). 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. In 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023 (pp. 112-114). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2023-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC42615.2023.10067348

Ye, Bingyi ; Wu, Guangdong ; Gai, Weixin et al. / 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. pp. 112-114 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS",

abstract = "The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time feed-forward equalizers (FFEs) in receivers (RXs) break the timing loop and compensate for electrical and optical impairments [2-3]. However, it relies on accurate, multiphase, and high-speed sampling clocks. The RX FFEs implemented in the continuous-time domain use active [4-5] or passive [5-6] delay lines, which eliminate clock and interleaved sample-and-hold circuits. In addition, the continuous-time FFE preserves edge information and therefore supports the oversampling clock and data recovery (CDR). This paper presents a 5-tap delay-line-based receiver FFE operating at 200Gb/s and equalizing a 17.2dB-loss channel.",

author = "Bingyi Ye and Guangdong Wu and Weixin Gai and Kai Sheng and Yandong He",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023 ; Conference date: 19-02-2023 Through 23-02-2023",

year = "2023",

doi = "10.1109/ISSCC42615.2023.10067348",

language = "英语",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "112--114",

booktitle = "2023 IEEE International Solid-State Circuits Conference, ISSCC 2023",

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Ye, B, Wu, G, Gai, W, Sheng, K & He, Y 2023, 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. in 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2023-February, Institute of Electrical and Electronics Engineers Inc., pp. 112-114, 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023, Virtual, Online, United States, 19/02/23. https://doi.org/10.1109/ISSCC42615.2023.10067348

6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. / Ye, Bingyi; Wu, Guangdong; Gai, Weixin et al.
2023 IEEE International Solid-State Circuits Conference, ISSCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 112-114 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2023-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ye, Bingyi

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AU - Sheng, Kai

AU - He, Yandong

PY - 2023

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AB - The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time feed-forward equalizers (FFEs) in receivers (RXs) break the timing loop and compensate for electrical and optical impairments [2-3]. However, it relies on accurate, multiphase, and high-speed sampling clocks. The RX FFEs implemented in the continuous-time domain use active [4-5] or passive [5-6] delay lines, which eliminate clock and interleaved sample-and-hold circuits. In addition, the continuous-time FFE preserves edge information and therefore supports the oversampling clock and data recovery (CDR). This paper presents a 5-tap delay-line-based receiver FFE operating at 200Gb/s and equalizing a 17.2dB-loss channel.

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ER -

Ye B, Wu G, Gai W, Sheng K, He Y. 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. In 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 112-114. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC42615.2023.10067348

6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

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