10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technology

Yinhang Zhang; Chao Yin; Xi Yang; Yongzheng Zhan

doi:10.1016/j.mejo.2024.106530

10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technology

Yinhang Zhang^*, Chao Yin, Xi Yang, Yongzheng Zhan

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

A Duobinary transmitter has been realized in this paper. The combination of high-frequency compensation characteristics of 6-tap feed forward equalizer (FFE) and high frequency attenuation characteristics of FR4 backplane is used to generate duobinary signal. 5-Stage calibrated delay unit with source capacitance degeneration is used to achieve a delay of 100 ps. The load resistance, source resistance and source capacitor are used to improve the flatness of group delay of delay unit. A prototype chip fabricated using 180 nm CMOS process has an area of 0.544 mm² with an energy efficiency of 19.4 pJ/bit. Though 18-inch FR4 backplane whose insertion loss is 16.5 dB, Duobinary signal with an opening degree of 45 mV can be obtained.

Original language	English
Article number	106530
Journal	Microelectronics Journal
Volume	156
DOIs	https://doi.org/10.1016/j.mejo.2024.106530
State	Published - Feb 2025
Externally published	Yes

Keywords

Duobinary
Eye diagram
Feed forward equalizer
Group delay

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1016/j.mejo.2024.106530

Cite this

@article{cd8cf3b8a8c247b5903b2c7f092c8b25,

title = "10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technology",

abstract = "A Duobinary transmitter has been realized in this paper. The combination of high-frequency compensation characteristics of 6-tap feed forward equalizer (FFE) and high frequency attenuation characteristics of FR4 backplane is used to generate duobinary signal. 5-Stage calibrated delay unit with source capacitance degeneration is used to achieve a delay of 100 ps. The load resistance, source resistance and source capacitor are used to improve the flatness of group delay of delay unit. A prototype chip fabricated using 180 nm CMOS process has an area of 0.544 mm2 with an energy efficiency of 19.4 pJ/bit. Though 18-inch FR4 backplane whose insertion loss is 16.5 dB, Duobinary signal with an opening degree of 45 mV can be obtained.",

keywords = "Duobinary, Eye diagram, Feed forward equalizer, Group delay",

author = "Yinhang Zhang and Chao Yin and Xi Yang and Yongzheng Zhan",

note = "Publisher Copyright: {\textcopyright} 2024",

year = "2025",

month = feb,

doi = "10.1016/j.mejo.2024.106530",

language = "英语",

volume = "156",

journal = "Microelectronics Journal",

issn = "0959-8324",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - 10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technology

AU - Zhang, Yinhang

AU - Yin, Chao

AU - Yang, Xi

AU - Zhan, Yongzheng

PY - 2025/2

Y1 - 2025/2

N2 - A Duobinary transmitter has been realized in this paper. The combination of high-frequency compensation characteristics of 6-tap feed forward equalizer (FFE) and high frequency attenuation characteristics of FR4 backplane is used to generate duobinary signal. 5-Stage calibrated delay unit with source capacitance degeneration is used to achieve a delay of 100 ps. The load resistance, source resistance and source capacitor are used to improve the flatness of group delay of delay unit. A prototype chip fabricated using 180 nm CMOS process has an area of 0.544 mm2 with an energy efficiency of 19.4 pJ/bit. Though 18-inch FR4 backplane whose insertion loss is 16.5 dB, Duobinary signal with an opening degree of 45 mV can be obtained.

AB - A Duobinary transmitter has been realized in this paper. The combination of high-frequency compensation characteristics of 6-tap feed forward equalizer (FFE) and high frequency attenuation characteristics of FR4 backplane is used to generate duobinary signal. 5-Stage calibrated delay unit with source capacitance degeneration is used to achieve a delay of 100 ps. The load resistance, source resistance and source capacitor are used to improve the flatness of group delay of delay unit. A prototype chip fabricated using 180 nm CMOS process has an area of 0.544 mm2 with an energy efficiency of 19.4 pJ/bit. Though 18-inch FR4 backplane whose insertion loss is 16.5 dB, Duobinary signal with an opening degree of 45 mV can be obtained.

KW - Duobinary

KW - Eye diagram

KW - Feed forward equalizer

KW - Group delay

UR - https://www.scopus.com/pages/publications/85211696139

U2 - 10.1016/j.mejo.2024.106530

DO - 10.1016/j.mejo.2024.106530

M3 - 文章

AN - SCOPUS:85211696139

SN - 0959-8324

VL - 156

JO - Microelectronics Journal

JF - Microelectronics Journal

M1 - 106530

ER -

10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technology

Abstract

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this