一款8 bit 480 MS/s逐次逼近型模数转换器

A single-channel 8 bit 480 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) fabricated via 55 nm CMOS technology was presented. A dual-loop structure including an asynchronous clock loop and a data loop was exploited in the proposed high-speed SAR ADC. A dynamic comparator with reset switches was developed to shorten the reset time and improve the comparison accuracy. A reversed monotonic switching sequence approach was proposed to improve the working speed of ADC and mitigate comparator speed degradation due to decreasing input common-mode voltage. The measurement results show that the ADC achieves a FOM_S of 147.3 dB, a SNDR of 42.7 dB and a SFDR of 50.53 dB under 100 MHz input signal, while consuming 6.9 mA current under 1.2 V power supply. The ADC core occupies 0.098 mm² area.